1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having an echo back comparison function.
2. Description of the Background Art
A collision detect method is one of the methods of controlling bus competition generated in a network capable of interchanging information between a plurality of devices connected to an external bus. In the collision detect method, each of the devices connected to the external bus outputs a transmission data indicative of the priority of its own to the external bus. The data outputted to the external bus is echoed back, that is, is inputted to each of the devices as a reception data. When the comparison between the transmission and reception data results in disagreement, the transmission of the data is interrupted. For execution of the collision detect method, a communication LSI having an echo back comparison function is needed.
FIG. 6 is a block diagram of the internal structure of a transmitter-receiver portion of a conventional communication LSI having the echo back comparison function. The transmitter-receiver portion comprises a transmitter portion 1, a receiver portion 2 and a comparison portion 3. The transmitter portion 1 is connected to the receiver portion 2 through an external serial bus 4.
The transmitter portion 1 includes a transmission buffer register 11, a P-to-S (parallel to serial) shift register 12, a PWM (pulse width modulator) portion 13, and a transmission buffer 14. A transmission buffer register address A1 indicative of a serial bus to the transmission buffer register 11, which transfers a 1-byte transmission data out of the transmission buffer register address A1 to the P-to-S shift register 12 in parallel. The P-to-S shift register 12 shifts the inputted 1-byte transmission data sequentially, to thereby serially output a serial data D1 to the PWM portion 13 in due order. The PWM portion 13 performs pulse width modulation on the serial data D1 to output a modulated serial data D2 to the transmission buffer 14. The transmission buffer 14 buffers the modulated serial data D2 to output a modulated serial data D3 having the same information as the modulated serial data D2 to the serial bus 4. A transmission data load clock T1 and a P-to-S shift register clock T2 control the operation of the P-to-S shift register 12. A PWM clock T3 controls the operation of the PWM portion 13.
The receiver portion 2 includes a reception buffer register 21, a S-to-P (serial to parallel) shift register 22, a PWDM (pulse width demodulator) portion 23, a digital filter 24, and a reception buffer 25. The reception buffer 25 buffers a serial data on the serial bus 4 and outputs it to the digital filter 24. The digital filter 24 performs a filtering processing for cutting off noise components on the serial data outputted from the reception buffer 25, and outputs a serial data D4 to the PWDM portion 23. The PWDM portion 23 demodulates the serial data D4 to output a demodulated serial data D5 to the S-to-P shift register 22. The demodulated serial data D5 is serially inputted to the S-to-P shift register 22 in due order until a 1-byte reception data is formed. The 1-byte reception data is outputted from the S-to-P shift register 22 to the reception buffer register 21 in parallel. A digital filter clock T4 controls the operation of the digital filter 24. A PWDM clock T5 controls the operation of the PWDM portion 23. A S-to-P shift register clock T6 and a reception data load clock T10 control the operation of the S-to-P shift register 22. A reception buffer address A2 is applied to the reception buffer register 21.
The comparison portion 3 includes a transmission data comparing register 31, a reception data comparing register 32, and a comparator 33. While the serial data D1 outputted from the P-to-S shift register 12 of the transmitter portion 1 is serially inputted to the first latch of the transmission data comparing register 31, the data shift operation is performed in the transmission data comparing register 31. While the demodulated serial data D5 outputted from the PWDM portion 23 of the receiver portion 3 is serially inputted to the first latch of the reception data comparing register 32, the data shift operation is performed in the reception data comparing register 32. The comparator 3 compares the second latch data of the transmission data comparing register 31 with the first latch data of the reception data comparing register 32 to output an echo back data D9.
FIG. 7 is a timing chart of the echo back comparison operation of the communication LSI shown in FIG. 6. With reference to FIG. 7, the echo back comparison operation will be discussed hereinafter.
Initially, the transmission buffer register address A1 is stored in the transmission buffer register 11. Subsequently, the transmission data load clock T1 being inputted to the P-to-S shift register 12 becomes the H level. In the period in which the clock T1 is at the H level, the transmission buffer register 11 outputs the 1-byte transmission data indicated by the transmission buffer register address A1 to the P-to-S shift register 12 in parallel (assuming that 1 byte=8 bits).
The P-to-S shift register clock T2 becomes the H level. Triggered by the H level rising of the clock T2, the P-to-S shift register 12 shifts the data and serially outputs the most significant output bit data (MSB=B7) in the inputted 1-byte transmission data as serial data D1. Subsequently, the H level rising of the clock T2 triggers the shift operation of the P-to-S shift register 12, whereby the P-to-S shift register 12 serially outputs the second most to least significant output bit data (B6 to LSB=B0) in due order as serial data D1.
The PWM clock T3 becomes the H level. Triggered by the H level rising of the clock T3, the PWM portion 13 performs the pulse width modulation on the serial data D1 to output the modulated serial data D2 to the transmission buffer 14. Substantially simultaneously, the transmission buffer 14 outputs the modulated serial data D3 having the same information as the modulated serial data D2 to the serial bus 4.
A comparison portion clock T7 rises to the H level substantially simultaneously with the PWM clock T3. Triggered by the H level rising of the clock T7, the serial data D1 is serially inputted to the first latch of the transmission data comparing register 31. Subsequently, when triggered by the H level rising of the comparison portion clock T7, the latest serial data D1 is sequentially inputted to the first latch of the transmission data comparing register 31 while the previously inputted serial data D1 are shifted to the second and successive latches thereof. Only the first and second latch data S1 and S2 of the transmission data comparing register 31 are shown in FIG. 7.
The modulated serial data D3 on the serial bus 4 is transferred through the reception buffer 25 to the digital filter 24. Based on the digital filter clock T4, the digital filter 24 performs the filtering processing on the modulated serial data D3 to output the serial data D4 to the PWDM portion 23. Since the filtering processing requires the time t1, the output timing of the serial data D4 is delayed for the time t1 from the output timing of the modulated serial data D3.
The PWDM clock T5 produces an H level pulse. Based on the H level pulse of the clock T5, the PWDM portion 23 performs the pulse width demodulation on the serial data D4 to output the demodulated serial data D5 to the S-to-P shift register 22. The time t2 required for the demodulation processing is the delay time of the output timing of the demodulated serial data D5 from the output timing of the serial data D4.
The S-to-P shift register clock T6 rises to the H level. Triggered by the H level rising of the clock T6, the demodulated serial data D5 is serially inputted to the first latch of the S-to-P shift register 22. Subsequently, when triggered by the H level rising of the clock T6, the latest demodulated serial data D5 is serially inputted to the first latch of the S-to-P shift register 22 while the previously inputted data are shifted to the second and successive latches thereof.
After the input of the 1-byte reception data to the latches of the S-to-P shift register 22, the reception data load clock T10 rises to the H level (not shown in FIG. 7). Triggered by the H level rising of the clock T10, the S-to-P shift register 22 outputs the 1-byte reception data to the reception buffer register 21 in parallel.
In the comparison portion 3, the demodulated serial data D5 is inputted to the first latch of the reception data comparing register 32, when triggered by the H level rising of a reception data comparing register clock T8. Subsequently, when triggered by the H level rising of the reception data comparing register clock T8, the latest demodulated serial data D5 is sequentially inputted to the first latch of the reception data comparing register 32 while the previously inputted demodulated serial data D5 are shifted to the second and successive latches thereof. Only the first latch data R1 of the reception data comparing register 32 is shown in FIG. 7.
Triggered by the H level rising of a comparison portion clock T9, the comparator 33 compares the second latch data S2 of the transmission data comparing register 31 with the first latch data R1 of the reception data comparing register 32 to output the echo back data D9 as a result of the comparison.
In the comparison between the second latch data S2 of the transmission data comparing register 31 and the first latch data R1 of the reception data comparing register 32, consideration is given to the delay time (t1+t2) generated between the timing of the serial data D1 inputted to the transmission data comparing register 31 and the timing of the demodulated serial data D5 inputted to the reception data comparing register 32. This provides for the comparison of the corresponding output bit data (B7 (MSB) to BO (LSB)).
The conventional communication LSI having the echo back comparison function is structured as mentioned above. The echo back comparison operation is performed in consideration of the delay time between the transmission of the serial data by the transmitter portion 1 and the reception thereof by the receiver portion 2. The comparison portion 3 must be provided with two registers, that is, the transmission data comparing register 31 for holding the transmission serial data and the reception data comparing register 32 for holding the reception serial data. There has been a problem that the number of devices accordingly increases so that the chip size becomes large.